About: Design and Optimization of ColdFire CPU Arithmetic Logical Unit

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This article describes design of ColdFire microprocessor ALU (Arithmetic Logical Unit) in VHDL language and presents an optimization to obtain maximum performance in Xilinx Virtex IV FPGA. The basic function of ALU is explained. There are described the instructions which any ALU must handle and some possibility how to design it. The advantages and disadvantages of performance are obtained as well. This article describes design of ColdFire microprocessor ALU (Arithmetic Logical Unit) in VHDL language and presents an optimization to obtain maximum performance in Xilinx Virtex IV FPGA. The basic function of ALU is explained. There are described the instructions which any ALU must handle and some possibility how to design it. The advantages and disadvantages of performance are obtained as well. (en)
Title	Design and Optimization of ColdFire CPU Arithmetic Logical Unit Design and Optimization of ColdFire CPU Arithmetic Logical Unit (en)
skos:prefLabel	Design and Optimization of ColdFire CPU Arithmetic Logical Unit Design and Optimization of ColdFire CPU Arithmetic Logical Unit (en)
skos:notation	RIV/00216305:26220/09:PU80787!RIV10-MSM-26220___
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GD102/08/H027), Z(MSM0021630513)
http://linked.open...vai/riv/dodaniDat	2010
http://linked.open...aciTvurceVysledku	Adamec, Filip Frýza, Tomáš
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	309648
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/09:PU80787
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Arithmetic Logical Unit, VHDL, FPGA, instructions (en)
http://linked.open.../riv/klicoveSlovo	VHDL Arithmetic Logical Unit FPGA instructions
http://linked.open...ontrolniKodProRIV	[CF7E268C675F]
http://linked.open...v/mistoKonaniAkce	Lodz
http://linked.open...i/riv/mistoVydani	Lodz (Poland)
http://linked.open...i/riv/nazevZdroje	Proceedings of 16th International Conference Mixed Design of Integrated Circuits and Systems
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	Advanced Methods, Structures and Components of Electronic Wireless Communication
http://linked.open...UplatneniVysledku	2009
http://linked.open...iv/tvurceVysledku	Adamec, Filip Frýza, Tomáš
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2009-06-25 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Advanced Electronic Communication Systems and Technologies (ELCOM)
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Neuveden
https://schema.org/isbn	978-83-928756-0-4
http://localhost/t...ganizacniJednotka	26220

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