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Description
  • This article describes design of the 8-bit asynchronous microcontroller simulation model in VHDL. The model is created in ISE Foundation design tool and simulated in Modelsim tool. This model is a simple application example of asynchronous systems designed in synchronous design tools. The design process of creating asynchronous system with 4-phase bundled-data protocol and with matching delays is described in the article. The model is described in gate-level abstraction. The simulation waveform of the functional construction is the result of this article. Described construction covers only the simulation model. The next step would be creating synthesizable model to FPGA.
  • This article describes design of the 8-bit asynchronous microcontroller simulation model in VHDL. The model is created in ISE Foundation design tool and simulated in Modelsim tool. This model is a simple application example of asynchronous systems designed in synchronous design tools. The design process of creating asynchronous system with 4-phase bundled-data protocol and with matching delays is described in the article. The model is described in gate-level abstraction. The simulation waveform of the functional construction is the result of this article. Described construction covers only the simulation model. The next step would be creating synthesizable model to FPGA. (en)
Title
  • Asynchronous Microcontroller Simulation Model in VHDL
  • Asynchronous Microcontroller Simulation Model in VHDL (en)
skos:prefLabel
  • Asynchronous Microcontroller Simulation Model in VHDL
  • Asynchronous Microcontroller Simulation Model in VHDL (en)
skos:notation
  • RIV/00216305:26220/08:PU76587!RIV10-MSM-26220___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GD102/08/H027), Z(MSM0021630513)
http://linked.open...iv/cisloPeriodika
  • 11
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
  • Kováč, Michal
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 357217
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26220/08:PU76587
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • Asynchronous, Microcontroller, VHDL, FPGA (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...odStatuVydavatele
  • FR - Francouzská republika
http://linked.open...ontrolniKodProRIV
  • [3BEA230D52A3]
http://linked.open...i/riv/nazevZdroje
  • PROCEEDINGS OF WORLD ACADEMY OF SCIENCE, ENGINEERING AND TECHNOLOGY
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...v/svazekPeriodika
  • 35
http://linked.open...iv/tvurceVysledku
  • Kováč, Michal
http://linked.open...n/vavai/riv/zamer
issn
  • 2070-3740
number of pages
http://localhost/t...ganizacniJednotka
  • 26220
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