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  • The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process .
  • The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process . (en)
  • Článek popisuje návrh a vývoj fázového závěsu, který je určen pro synchronizaci s modulátorem sigma-delta. (cs)
Title
  • Design of Integer Phase Locked Loop
  • Design of Integer Phase Locked Loop (en)
  • Návrh a vývoj fázového závěsu (cs)
skos:prefLabel
  • Design of Integer Phase Locked Loop
  • Design of Integer Phase Locked Loop (en)
  • Návrh a vývoj fázového závěsu (cs)
skos:notation
  • RIV/00216305:26220/07:PU71518!RIV08-GA0-26220___
http://linked.open.../vavai/riv/strany
  • 27-33
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  • P(GA102/05/0869), Z(MSM0021630503)
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  • 416424
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  • RIV/00216305:26220/07:PU71518
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  • phase locked-loop (en)
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  • [DD88D710327F]
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  • BRNO
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  • Brno
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  • MIKROSYN. Nové trendy v mikroelektronických systémech a nanotechnologiích.. Seminář o výsledcích výzkumného záměru MSM 0021630503 v roce 2007. Sborník příspěvků
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  • Fujcik, Lukáš
  • Háze, Jiří
  • Prokop, Roman
  • Vrba, Radimír
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http://linked.open.../riv/zahajeniAkce
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number of pages
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  • Ing. Zdeněk Novotný CSc.
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  • 978-80-214-3534-6
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  • 26220
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