About: Two Level Testability System

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Principles of two level testability analysis system will are described in the paper. The behavioural description of the unit under analysis (UUA) is the first level, on which the source VHDL file is taken as an input. On this level, the VHDL constructions which might cause testability problems in the resulting design are identified and the possibility of deriving i paths is evaluated. The RT level is the second level, on which the testability aspects are taken into account. For these purposes, the RT leevel structure is converted into a directed labelled graph which reflects the structure of the UUA and its diagnostic features which are important for the testability analysis. The analysis is done on the graph instead of on the VHDL source text. Principles of two level testability analysis system will are described in the paper. The behavioural description of the unit under analysis (UUA) is the first level, on which the source VHDL file is taken as an input. On this level, the VHDL constructions which might cause testability problems in the resulting design are identified and the possibility of deriving i paths is evaluated. The RT level is the second level, on which the testability aspects are taken into account. For these purposes, the RT leevel structure is converted into a directed labelled graph which reflects the structure of the UUA and its diagnostic features which are important for the testability analysis. The analysis is done on the graph instead of on the VHDL source text. (en)
Title	Two Level Testability System Two Level Testability System (en)
skos:prefLabel	Two Level Testability System Two Level Testability System (en)
skos:notation	RIV/00216305:26220/01:PU28700!RIV/2002/GA0/262202/N
http://linked.open.../vavai/riv/strany	433-440
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/01/1531), Z(MSM 262200012)
http://linked.open...vai/riv/dodaniDat	2002
http://linked.open...aciTvurceVysledku	Kotásek, Zdeněk Růžička, Richard Strnadel, Josef Zbořil, František
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	699339
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/01:PU28700
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	RTL, Testability Analysis, VHDL (en)
http://linked.open.../riv/klicoveSlovo	Testability Analysis VHDL RTL
http://linked.open...ontrolniKodProRIV	[91973A3BD81A]
http://linked.open...v/mistoKonaniAkce	Hradec nad Moravicí
http://linked.open...i/riv/mistoVydani	Ostrava
http://linked.open...i/riv/nazevZdroje	Proceedings of the 35th Spring International Conference MOSIS'01
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	4 (xsd:int)
http://linked.open...cetTvurcuVysledku	4 (xsd:int)
http://linked.open...ocetUcastnikuAkce	0 (xsd:int)
http://linked.open...nichUcastnikuAkce	0 (xsd:int)
http://linked.open...vavai/riv/projekt	Formal approaches in digital circuit diagnostics - testable design verification
http://linked.open...UplatneniVysledku	2001
http://linked.open...iv/tvurceVysledku	Kotásek, Zdeněk Růžička, Richard Strnadel, Josef Zbořil, František
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2001-05-09 (xsd:date)
http://linked.open...n/vavai/riv/zamer	http://linked.opendata.cz/resource/domain/vavai/zamer/MSM%20262200012
number of pages	8 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Neuveden
https://schema.org/isbn	80-85988-57-7
http://localhost/t...ganizacniJednotka	26220

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