About: Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation

Facets (new session)
Description
Metadata
Settings
- owl:sameAs
- Inference Rule:

About: Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation Goto Sponge NotDistinct Permalink

An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

Attributes	Values
rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This paper presents Hardware in the Loop (HIL) simulation of the BLDC motor used in aerospace applications. Due to a high frequency driving signals and a high dynamics of the electrical part of the BLDC motor, the utilization of FPGA is necessary. The algorithm is distributed between the CPU and the FPGA and targeted to dSPACE modular hardware. This paper presents Hardware in the Loop (HIL) simulation of the BLDC motor used in aerospace applications. Due to a high frequency driving signals and a high dynamics of the electrical part of the BLDC motor, the utilization of FPGA is necessary. The algorithm is distributed between the CPU and the FPGA and targeted to dSPACE modular hardware. (en)
Title	Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation (en)
skos:prefLabel	Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation (en)
skos:notation	RIV/00216305:26210/13:PU108434!RIV14-MSM-26210___
http://linked.open...avai/riv/aktivita	R
http://linked.open...avai/riv/aktivity	R
http://linked.open...vai/riv/dodaniDat	2014
http://linked.open...aciTvurceVysledku	Grepl, Robert Sova, Václav
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta strojního inženýrství
http://linked.open...dnocenehoVysledku	77059
http://linked.open...ai/riv/idVysledku	RIV/00216305:26210/13:PU108434
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	BLDC, HIL, FPGA (en)
http://linked.open.../riv/klicoveSlovo	BLDC FPGA HIL
http://linked.open...ontrolniKodProRIV	[D78027ECA907]
http://linked.open...v/mistoKonaniAkce	Brno
http://linked.open...i/riv/mistoVydani	Cham, Heidelberg, New York, Dordrecht, London
http://linked.open...i/riv/nazevZdroje	Mechatronics 2013: Recent Technological and Scientific Advances
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...UplatneniVysledku	2013
http://linked.open...iv/tvurceVysledku	Grepl, Robert Sova, Václav
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2013-10-07 (xsd:date)
number of pages	8 (xsd:int)
http://bibframe.org/vocab/doi	10.1007/978-3-319-02294-9_84
http://purl.org/ne...btex#hasPublisher	Springer International Publishing
https://schema.org/isbn	978-3-319-02293-2
http://localhost/t...ganizacniJednotka	26210

Faceted Search & Find service v1.16.118 as of Jun 21 2024

Alternative Linked Data Documents: ODE Content Formats:

RDF

ODATA

Microdata

About

OpenLink Virtuoso version 07.20.3240 as of Jun 21 2024, on Linux (x86_64-pc-linux-gnu), Single-Server Edition (126 GB total memory, 58 GB memory in use)
Data on this page belongs to its respective rights holders.
Virtuoso Faceted Browser Copyright © 2009-2024 OpenLink Software