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Description
  • This technical report analyzes the process of verification of hardware design in Liberouter project. Such an analysis had become a necessity since we had developed several tools that were difficult both to maintain and modify. This document tries to sum up our needs and to propose a way our tools could be organized. Description of verification environment Verunka is given in more detail as it is a new tool.
  • This technical report analyzes the process of verification of hardware design in Liberouter project. Such an analysis had become a necessity since we had developed several tools that were difficult both to maintain and modify. This document tries to sum up our needs and to propose a way our tools could be organized. Description of verification environment Verunka is given in more detail as it is a new tool. (en)
  • Tato zpráva analizuje proces verifikace hardwarového návrhu v projektu Liberouter. Popisuje nástroje převodu specifikace modelu i pomocné nástroje pro řízení vlastní verifikace (náš vlastní script Verunka). (cs)
Title
  • Verification Process of Hardware Design in Liberouter Project
  • Verification Process of Hardware Design in Liberouter Project (en)
  • Proces verifikace hardwarového návrhu v projektu Liberouter (cs)
skos:prefLabel
  • Verification Process of Hardware Design in Liberouter Project
  • Verification Process of Hardware Design in Liberouter Project (en)
  • Proces verifikace hardwarového návrhu v projektu Liberouter (cs)
skos:notation
  • RIV/00216224:14330/04:00010547!RIV08-MSM-14330___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA201/03/0509), Z(MSM 000000001), Z(MSM 143300001), Z(MSM6383917201)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 592337
http://linked.open...ai/riv/idVysledku
  • RIV/00216224:14330/04:00010547
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • formal verification; Liberouter; Cadence SMV; VHDL (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...i/riv/kodPristupu
http://linked.open...ontrolniKodProRIV
  • [2AD0A783F0E7]
http://linked.open...i/riv/mistoVydani
  • Praha
http://linked.open...telVyzkumneZpravy
  • CESNET z.s.p.o.
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Holeček, Jan
  • Šafránek, David
  • Šimeček, Pavel
  • Řehák, Vojtěch
  • Kratochvíla, Tomáš
http://linked.open...rzeVyzkumneZpravy
  • CESNET Technical Report No. 05/2004
http://linked.open...n/vavai/riv/zamer
http://localhost/t...ganizacniJednotka
  • 14330
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