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Description
  • V této zprávě nahlížíme z formálního hlediska na HW design pro FPGA čipy a modelujeme ho jako Kripkeho strukturu. Dále je zde zpracován problém společného modelování synchronních a asynchronních částí designu. (cs)
  • In this report, a formal view of an FPGA hardware design is presented. An approach of how elementary FPGA design entities can be modeled in terms of Kripke structures is presented here. The report is also focused on capturing the problems of modeling synchronous parts of hardware design together with its asynchronous parts.
  • In this report, a formal view of an FPGA hardware design is presented. An approach of how elementary FPGA design entities can be modeled in terms of Kripke structures is presented here. The report is also focused on capturing the problems of modeling synchronous parts of hardware design together with its asynchronous parts. (en)
Title
  • How to Formalize FPGA Hardware Design
  • How to Formalize FPGA Hardware Design (en)
  • Kterak formalizovat hardwarový design FPGA čipů (cs)
skos:prefLabel
  • How to Formalize FPGA Hardware Design
  • How to Formalize FPGA Hardware Design (en)
  • Kterak formalizovat hardwarový design FPGA čipů (cs)
skos:notation
  • RIV/00216224:14330/04:00010387!RIV08-MSM-14330___
http://linked.open...avai/riv/aktivita
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  • P(GA201/03/0509), Z(MSM 000000001), Z(MSM 143300001), Z(MSM6383917201)
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  • 566750
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  • RIV/00216224:14330/04:00010387
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  • formal verification; programmable hardware; FPGA; Cadence SMV; VHDL (en)
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  • [37EF94C4110D]
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  • Praha
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  • CESNET, z.s.p.o.
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  • Holeček, Jan
  • Šafránek, David
  • Šimeček, Pavel
  • Řehák, Vojtěch
  • Kratochvíla, Tomáš
http://linked.open...rzeVyzkumneZpravy
  • CESNET Technical Report No. 04/2004
http://linked.open...n/vavai/riv/zamer
http://localhost/t...ganizacniJednotka
  • 14330
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