| Attributes | Values |
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| rdf:type
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| Description
| - Current hardware acceleration cores for network traffic processing are often well optimized for one particular task and therefore provide high level of hardware acceleration. But for many applications, such as network traffic monitoring and security, it is also necessary to achieve rapid development cycle to provide fast response to security threats. We propose and evaluate a new concept of hardware acceleration for flexible flow-based network traffic monitoring with support of application protocol analysis. The concept is called Software Defined Monitoring (SDM) and it relies on a configurable hardware accelerator implemented in FPGA, coupled with smart monitoring tasks running as software on general CPU. The monitoring tasks in the software control the level of detail and type of information retained during the hardware processing. This arrangement allows rapid application prototyping in the software, followed by further shifting of the timing critical parts of the processing to the hardware accelerator. The concept is proposed with the scalability in mind, therefore it is suitable for different FPGA based platforms ranging from embedded single-chip solutions (such as Zynq or Cyclone V) to high-speed backbone network monitoring boxes. Our pilot high-speed implementation using FPGA acceleration board in a commodity server performs a 100 Gb/s flow traffic measurement augmented by a selected application protocol analysis.
- Current hardware acceleration cores for network traffic processing are often well optimized for one particular task and therefore provide high level of hardware acceleration. But for many applications, such as network traffic monitoring and security, it is also necessary to achieve rapid development cycle to provide fast response to security threats. We propose and evaluate a new concept of hardware acceleration for flexible flow-based network traffic monitoring with support of application protocol analysis. The concept is called Software Defined Monitoring (SDM) and it relies on a configurable hardware accelerator implemented in FPGA, coupled with smart monitoring tasks running as software on general CPU. The monitoring tasks in the software control the level of detail and type of information retained during the hardware processing. This arrangement allows rapid application prototyping in the software, followed by further shifting of the timing critical parts of the processing to the hardware accelerator. The concept is proposed with the scalability in mind, therefore it is suitable for different FPGA based platforms ranging from embedded single-chip solutions (such as Zynq or Cyclone V) to high-speed backbone network monitoring boxes. Our pilot high-speed implementation using FPGA acceleration board in a commodity server performs a 100 Gb/s flow traffic measurement augmented by a selected application protocol analysis. (en)
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| Title
| - Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring
- Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring (en)
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| skos:prefLabel
| - Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring
- Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring (en)
|
| skos:notation
| - RIV/63839172:_____/14:10130393!RIV15-MSM-63839172
|
| http://linked.open...avai/riv/aktivita
| |
| http://linked.open...avai/riv/aktivity
| - P(ED1.1.00/02.0070), P(LM2010005), S
|
| http://linked.open...vai/riv/dodaniDat
| |
| http://linked.open...aciTvurceVysledku
| |
| http://linked.open.../riv/druhVysledku
| |
| http://linked.open...iv/duvernostUdaju
| |
| http://linked.open...titaPredkladatele
| |
| http://linked.open...dnocenehoVysledku
| |
| http://linked.open...ai/riv/idVysledku
| - RIV/63839172:_____/14:10130393
|
| http://linked.open...riv/jazykVysledku
| |
| http://linked.open.../riv/klicovaSlova
| - L7; Application protocols; Acceleration; Monitoring; FPGA (en)
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| http://linked.open.../riv/klicoveSlovo
| |
| http://linked.open...ontrolniKodProRIV
| |
| http://linked.open...v/mistoKonaniAkce
| |
| http://linked.open...i/riv/mistoVydani
| |
| http://linked.open...i/riv/nazevZdroje
| - 2014 24th International Conference on Field Programmable Logic and Applications (FPL 2014)
|
| http://linked.open...in/vavai/riv/obor
| |
| http://linked.open...ichTvurcuVysledku
| |
| http://linked.open...cetTvurcuVysledku
| |
| http://linked.open...vavai/riv/projekt
| |
| http://linked.open...UplatneniVysledku
| |
| http://linked.open...iv/tvurceVysledku
| - Kořenek, Jan
- Puš, Viktor
- Benáček, Pavel
- Kekely, Lukáš
|
| http://linked.open...vavai/riv/typAkce
| |
| http://linked.open.../riv/zahajeniAkce
| |
| number of pages
| |
| http://purl.org/ne...btex#hasPublisher
| - IEEE Circuits and Systems Society
|
| https://schema.org/isbn
| |
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