About: Design Methodology of Configurable High Performance Packet Parser for FPGA

Facets (new session)
Description
Metadata
Settings
- owl:sameAs
- Inference Rule:

About: Design Methodology of Configurable High Performance Packet Parser for FPGA Goto Sponge NotDistinct Permalink

An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

Attributes	Values
rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols. Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols. (en)
Title	Design Methodology of Configurable High Performance Packet Parser for FPGA Design Methodology of Configurable High Performance Packet Parser for FPGA (en)
skos:prefLabel	Design Methodology of Configurable High Performance Packet Parser for FPGA Design Methodology of Configurable High Performance Packet Parser for FPGA (en)
skos:notation	RIV/63839172:_____/14:10130332!RIV15-MSM-63839172
http://linked.open...avai/riv/aktivita	P S
http://linked.open...avai/riv/aktivity	P(ED1.1.00/02.0070), P(LM2010005), S
http://linked.open...vai/riv/dodaniDat	2015
http://linked.open...aciTvurceVysledku	Kekely, Lukáš Kořenek, Jan Puš, Viktor
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	CESNET - zájmové sdružení právnických osob
http://linked.open...dnocenehoVysledku	10439
http://linked.open...ai/riv/idVysledku	RIV/63839172:_____/14:10130332
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	FPGA; Latency; Packet Parsing (en)
http://linked.open.../riv/klicoveSlovo	Latency FPGA Packet Parsing
http://linked.open...ontrolniKodProRIV	[FF747A4223DA]
http://linked.open...v/mistoKonaniAkce	Warsaw, Poland
http://linked.open...i/riv/mistoVydani	Warsaw, Poland
http://linked.open...i/riv/nazevZdroje	2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
http://linked.open...in/vavai/riv/obor	IN
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	IT4Innovations Centre of Excellence Large Infrastructure CESNET
http://linked.open...UplatneniVysledku	2014
http://linked.open...iv/tvurceVysledku	Kořenek, Jan Puš, Viktor Kekely, Lukáš
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open...ain/vavai/riv/wos	000346734200038
http://linked.open.../riv/zahajeniAkce	2014-04-22 (xsd:date)
issn	2334-3133
number of pages	6 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-1-4799-4558-0

Faceted Search & Find service v1.16.118 as of Jun 21 2024

Alternative Linked Data Documents: ODE Content Formats:

RDF

ODATA

Microdata

About

OpenLink Virtuoso version 07.20.3240 as of Jun 21 2024, on Linux (x86_64-pc-linux-gnu), Single-Server Edition (126 GB total memory, 77 GB memory in use)
Data on this page belongs to its respective rights holders.
Virtuoso Faceted Browser Copyright © 2009-2024 OpenLink Software