About: Hardware Architecture for the Fast Pattern Matching

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	As the speed of current computer networks in- creases, it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. As attacks on modern networks became more and more complex, it is necessity to detect attack placed not only in single packet but at the level of network flows. Pattern matching in the network flows is the time-critical operation of many modern IDS. Most of the regularly used patterns are described by the regular expression. This work describes advanced hardware architecture for the fast regular expression matching based on the perfect hashing. The proposed architecture is scalable and can achieve multigigabit throughput per network flow. As the speed of current computer networks in- creases, it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. As attacks on modern networks became more and more complex, it is necessity to detect attack placed not only in single packet but at the level of network flows. Pattern matching in the network flows is the time-critical operation of many modern IDS. Most of the regularly used patterns are described by the regular expression. This work describes advanced hardware architecture for the fast regular expression matching based on the perfect hashing. The proposed architecture is scalable and can achieve multigigabit throughput per network flow. (en)
Title	Hardware Architecture for the Fast Pattern Matching Hardware Architecture for the Fast Pattern Matching (en)
skos:prefLabel	Hardware Architecture for the Fast Pattern Matching Hardware Architecture for the Fast Pattern Matching (en)
skos:notation	RIV/00216305:26230/13:PU106307!RIV14-MSM-26230___
http://linked.open...avai/predkladatel	Fakulta informačních technologií
http://linked.open...avai/riv/aktivita	S Z
http://linked.open...avai/riv/aktivity	S, Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2014
http://linked.open...aciTvurceVysledku	Kořenek, Jan Kaštil, Jan Košař, Vlastimil
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	77056
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/13:PU106307
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	pattern matching, intrussion detection system, regular expression, FPGA (en)
http://linked.open.../riv/klicoveSlovo	pattern matching regular expression FPGA intrussion detection system
http://linked.open...ontrolniKodProRIV	[CCFBDE4DC23D]
http://linked.open...v/mistoKonaniAkce	Karlovy Vary
http://linked.open...i/riv/mistoVydani	Brno
http://linked.open...i/riv/nazevZdroje	2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...UplatneniVysledku	2013
http://linked.open...iv/tvurceVysledku	Kaštil, Jan Kořenek, Jan Košař, Vlastimil
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2013-04-08 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-1-4673-6133-0
http://localhost/t...ganizacniJednotka	26230

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