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Description
  • NetFPGA-1G has shown its potential in enabling fast traffic processing while introducing no packet loss and minimal delay. Now it is time to scale down in order to enable a massive deployment of the FPGA solutions in networking. We propose and build a low-cost and low-power platform which is be capable of hosting embedded applications with FPGA support. Such a platform might enable faster deployment of new ideas in networking and might prove useful for large-scale experiments (stacks of platforms) as its size, power consumption and cost are expected to be ten times lower of the NetFPGA-cube. It is recognized that the FPGA coupled with the host processor comprises a powerful platform for network traffic processing. The logic of such a solution is clear. Computational intensive tasks are handled by the FPGA logic whereas more complex tasks by the processor. The proposed platform aims at such a design in which the FPGA and the processor are even more tightly coupled together on a single die S
  • NetFPGA-1G has shown its potential in enabling fast traffic processing while introducing no packet loss and minimal delay. Now it is time to scale down in order to enable a massive deployment of the FPGA solutions in networking. We propose and build a low-cost and low-power platform which is be capable of hosting embedded applications with FPGA support. Such a platform might enable faster deployment of new ideas in networking and might prove useful for large-scale experiments (stacks of platforms) as its size, power consumption and cost are expected to be ten times lower of the NetFPGA-cube. It is recognized that the FPGA coupled with the host processor comprises a powerful platform for network traffic processing. The logic of such a solution is clear. Computational intensive tasks are handled by the FPGA logic whereas more complex tasks by the processor. The proposed platform aims at such a design in which the FPGA and the processor are even more tightly coupled together on a single die S (en)
Title
  • A New Embedded Platform for Rapid Development of Networking Applications
  • A New Embedded Platform for Rapid Development of Networking Applications (en)
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  • A New Embedded Platform for Rapid Development of Networking Applications
  • A New Embedded Platform for Rapid Development of Networking Applications (en)
skos:notation
  • RIV/00216305:26230/12:PU101849!RIV13-MSM-26230___
http://linked.open...avai/predkladatel
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(ED1.1.00/02.0070), P(VG20102015022), S, Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
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http://linked.open...iv/duvernostUdaju
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  • 120361
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/12:PU101849
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • FPGA, Zynq, Embedded, Networking (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [404AC37C22FC]
http://linked.open...v/mistoKonaniAkce
  • Austin, TX
http://linked.open...i/riv/mistoVydani
  • Austin
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the 2012 Seventh ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2012)
http://linked.open...in/vavai/riv/obor
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http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Korček, Pavol
  • Kořenek, Jan
  • Žádník, Martin
  • Košař, Vlastimil
  • Viktorin, Jan
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://bibframe.org/vocab/doi
  • 10.1145/2396556.2396573
http://purl.org/ne...btex#hasPublisher
  • IEEE Computer Society
https://schema.org/isbn
  • 978-1-4503-1684-2
http://localhost/t...ganizacniJednotka
  • 26230
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