About: Hardware Architecture for Packet Classification with Prefix Coloring

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Packet classification is a widely used operation in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays algorithms implemented in hardware can achieve multigigabit speeds, but suffer with great memory overhead. We propose a new algorithm and hardware architecture which reduces memory requirements of decomposition based methods for packet classification. The algorithm uses prefix coloring to reduce large amount of Cartesian product rules at the cost of an additional pipelined processing and a few bits added into results of the longest prefix match operation. The proposed hardware architecture is designed as a processing pipeline with the throughput of 266 million packets per second using commodity FPGA and one external memory. The greatest strength of the algorithm is the constant time complexity of the search operation, which makes the solution resistant to various classes of netw Packet classification is a widely used operation in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays algorithms implemented in hardware can achieve multigigabit speeds, but suffer with great memory overhead. We propose a new algorithm and hardware architecture which reduces memory requirements of decomposition based methods for packet classification. The algorithm uses prefix coloring to reduce large amount of Cartesian product rules at the cost of an additional pipelined processing and a few bits added into results of the longest prefix match operation. The proposed hardware architecture is designed as a processing pipeline with the throughput of 266 million packets per second using commodity FPGA and one external memory. The greatest strength of the algorithm is the constant time complexity of the search operation, which makes the solution resistant to various classes of netw (en)
Title	Hardware Architecture for Packet Classification with Prefix Coloring Hardware Architecture for Packet Classification with Prefix Coloring (en)
skos:prefLabel	Hardware Architecture for Packet Classification with Prefix Coloring Hardware Architecture for Packet Classification with Prefix Coloring (en)
skos:notation	RIV/00216305:26230/11:PU96017!RIV12-MSM-26230___
http://linked.open...avai/predkladatel	Fakulta informačních technologií
http://linked.open...avai/riv/aktivita	Z
http://linked.open...avai/riv/aktivity	Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2012
http://linked.open...aciTvurceVysledku	Kořenek, Jan Puš, Viktor Kajan, Michal
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	201732
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/11:PU96017
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	FPGA, SRAM, hardware, parallelism, classification (en)
http://linked.open.../riv/klicoveSlovo	FPGA classification parallelism SRAM hardware
http://linked.open...ontrolniKodProRIV	[5D84BCAF56C0]
http://linked.open...v/mistoKonaniAkce	Cottbus
http://linked.open...i/riv/mistoVydani	Cottbus
http://linked.open...i/riv/nazevZdroje	IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...UplatneniVysledku	2011
http://linked.open...iv/tvurceVysledku	Kajan, Michal Kořenek, Jan Puš, Viktor
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2011-04-13 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	6 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-1-4244-9753-9
http://localhost/t...ganizacniJednotka	26230

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