About: Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	With the increased amount of data transferred by<br>computer networks, the amount of the malicious traffic also<br>increases and therefore it is necessary to protect networks<br>by security systems such as firewalls and Intrusion Detection<br>Systems (IDS) operating at multigigabit speeds. Pattern matching<br>is the time critical operation of current IDS. This paper deals<br>with the analysis of regular expressions used by modern IDS<br>to describe malicious traffic. According to our analysis, more<br>than 64 percent of regular expressions create Deterministic Finite<br>Automaton (DFA) with less than 20 percent of saturation of<br>the transition table which allows efficient implementation of<br>pattern matching into FPGA platform. We propose architecture<br>for fast pattern matching using perfect hashing suitable for<br>implementation into FPGA platform. The memory requirements<br>of presented architecture is closed to the theoretical minimum<br>for sparse transition tables. With the increased amount of data transferred by<br>computer networks, the amount of the malicious traffic also<br>increases and therefore it is necessary to protect networks<br>by security systems such as firewalls and Intrusion Detection<br>Systems (IDS) operating at multigigabit speeds. Pattern matching<br>is the time critical operation of current IDS. This paper deals<br>with the analysis of regular expressions used by modern IDS<br>to describe malicious traffic. According to our analysis, more<br>than 64 percent of regular expressions create Deterministic Finite<br>Automaton (DFA) with less than 20 percent of saturation of<br>the transition table which allows efficient implementation of<br>pattern matching into FPGA platform. We propose architecture<br>for fast pattern matching using perfect hashing suitable for<br>implementation into FPGA platform. The memory requirements<br>of presented architecture is closed to the theoretical minimum<br>for sparse transition tables. (en)
Title	Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing (en)
skos:prefLabel	Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing (en)
skos:notation	RIV/00216305:26230/10:PU89524!RIV11-MSM-26230___
http://linked.open...avai/riv/aktivita	S Z
http://linked.open...avai/riv/aktivity	S, Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2011
http://linked.open...aciTvurceVysledku	Kořenek, Jan Kaštil, Jan
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	261204
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/10:PU89524
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Intrusion Detection, Perfect Hashing,hardware acceleration, Deterministic Finite Automata<br> (en)
http://linked.open.../riv/klicoveSlovo	Intrusion Detection hardware acceleration Deterministic Finite Automata<br> Perfect Hashing
http://linked.open...ontrolniKodProRIV	[51A3C6D8E3F5]
http://linked.open...v/mistoKonaniAkce	Vienna
http://linked.open...i/riv/mistoVydani	Vienna
http://linked.open...i/riv/nazevZdroje	Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...UplatneniVysledku	2010
http://linked.open...iv/tvurceVysledku	Kaštil, Jan Kořenek, Jan
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2010-04-14 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-1-4244-6610-8
http://localhost/t...ganizacniJednotka	26230

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