About: Memory Optimization for Packet Classification Algorithms in FPGA

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Packet classification algorithms are widely used in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays hardware architectures can achieve multigigabit speeds only at the cost of large data structures, which can not fit into the on-chip memory. We propose novel method how to reduce data structure size for the family of decomposition architectures at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the Cartesian product nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed. Packet classification algorithms are widely used in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays hardware architectures can achieve multigigabit speeds only at the cost of large data structures, which can not fit into the on-chip memory. We propose novel method how to reduce data structure size for the family of decomposition architectures at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the Cartesian product nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed. (en)
Title	Memory Optimization for Packet Classification Algorithms in FPGA Memory Optimization for Packet Classification Algorithms in FPGA (en)
skos:prefLabel	Memory Optimization for Packet Classification Algorithms in FPGA Memory Optimization for Packet Classification Algorithms in FPGA (en)
skos:notation	RIV/00216305:26230/10:PU89522!RIV14-MSM-26230___
http://linked.open...avai/riv/aktivita	Z
http://linked.open...avai/riv/aktivity	Z(MSM0021630528), Z(MSM6383917201)
http://linked.open...vai/riv/dodaniDat	2014
http://linked.open...aciTvurceVysledku	Kořenek, Jan Puš, Viktor
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	270328
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/10:PU89522
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	packet classification, sram, fpga, tcam (en)
http://linked.open.../riv/klicoveSlovo	fpga packet classification sram tcam
http://linked.open...ontrolniKodProRIV	[68B698A053FF]
http://linked.open...v/mistoKonaniAkce	Vienna
http://linked.open...i/riv/mistoVydani	Vídeň
http://linked.open...i/riv/nazevZdroje	Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
http://linked.open...in/vavai/riv/obor	IN
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...UplatneniVysledku	2010
http://linked.open...iv/tvurceVysledku	Kořenek, Jan Puš, Viktor
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2010-04-14 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti Optical National Research Network and Its New Applications
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-1-4244-6610-8
http://localhost/t...ganizacniJednotka	26230

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