| Attributes | Values |
|---|
| rdf:type
| |
| Description
| - Rozdělení aplikace mezi konvenční procesor a akcelerační kartu s FPGA čipy se ukázalo jako vhodný způsob pro akceleraci výpočetně náročných úloh. V těchto aplikacích, musí vyvojář obvykle implementovat propojovací systém mezi komponentami umístěnými v FPGA a systémovou sběrnicí. Tento úkol je však často komplikován různými požadavky ze strany uživatelských komponent např. na propustnost, latenci čtecích operací, potřeba DMA přenosů apod. Cílem této práce je ukázat nový přístup pro implementaci propojovacího systému a umožnit vývojáři se soustředit na vývoj cílové aplikace. Navrhovaný propojovací systém je založen na stromové architektuře, eliminuje citlivost na vzdálenost, podporuje připojení komponent s různými požadavky na propustnost, podporuje model rozdělených transakcí a mnoho dalších vlastností. Navrhovaný systém je implementován a ohodnocen na čipech s technologií Virtex 5.<br> (cs)
- The division of an application between a conventional processor and an acceleration card with FPGA chips has been proved as a suitable way for an acceleration of computationally intensive tasks. In such applications, the designer usually has to implement an interconnection between components placed in FPGA and the host system bus. This task is often complicated by different requirements of user components for throughput, latency of reading operations, need for DMA transfers etc. The objective of this work is to show a new approach for implementation of interconnection systems and to enable the designer to focus on the development of the target application. The proposed interconnection system is based on tree topology. The system eliminates the sensitivity of wide buses to the distance, supports the connection of components with different requirements for throughput, supports split transaction model and many other features. The proposed system is implemented and evaluated on chips with Virtex 5 t
- The division of an application between a conventional processor and an acceleration card with FPGA chips has been proved as a suitable way for an acceleration of computationally intensive tasks. In such applications, the designer usually has to implement an interconnection between components placed in FPGA and the host system bus. This task is often complicated by different requirements of user components for throughput, latency of reading operations, need for DMA transfers etc. The objective of this work is to show a new approach for implementation of interconnection systems and to enable the designer to focus on the development of the target application. The proposed interconnection system is based on tree topology. The system eliminates the sensitivity of wide buses to the distance, supports the connection of components with different requirements for throughput, supports split transaction model and many other features. The proposed system is implemented and evaluated on chips with Virtex 5 t (en)
|
| Title
| - GICS: Generic Interconnection System
- GICS: Generic Interconnection System (en)
- GICS: Generický propojovací systém (cs)
|
| skos:prefLabel
| - GICS: Generic Interconnection System
- GICS: Generic Interconnection System (en)
- GICS: Generický propojovací systém (cs)
|
| skos:notation
| - RIV/00216305:26230/08:PU78052!RIV09-MSM-26230___
|
| http://linked.open...avai/riv/aktivita
| |
| http://linked.open...avai/riv/aktivity
| - Z(MSM0021630528), Z(MSM6383917201)
|
| http://linked.open...vai/riv/dodaniDat
| |
| http://linked.open...aciTvurceVysledku
| |
| http://linked.open.../riv/druhVysledku
| |
| http://linked.open...iv/duvernostUdaju
| |
| http://linked.open...titaPredkladatele
| |
| http://linked.open...dnocenehoVysledku
| |
| http://linked.open...ai/riv/idVysledku
| - RIV/00216305:26230/08:PU78052
|
| http://linked.open...riv/jazykVysledku
| |
| http://linked.open.../riv/klicovaSlova
| - Interconnection system, PCI Express, FPGA<br> (en)
|
| http://linked.open.../riv/klicoveSlovo
| |
| http://linked.open...ontrolniKodProRIV
| |
| http://linked.open...v/mistoKonaniAkce
| |
| http://linked.open...i/riv/mistoVydani
| |
| http://linked.open...i/riv/nazevZdroje
| - 2008 International Conference on Field Programmable Logic and Applications
|
| http://linked.open...in/vavai/riv/obor
| |
| http://linked.open...ichTvurcuVysledku
| |
| http://linked.open...cetTvurcuVysledku
| |
| http://linked.open...UplatneniVysledku
| |
| http://linked.open...iv/tvurceVysledku
| - Martínek, Tomáš
- Kořenek, Jan
- Málek, Tomáš
|
| http://linked.open...vavai/riv/typAkce
| |
| http://linked.open.../riv/zahajeniAkce
| |
| http://linked.open...n/vavai/riv/zamer
| |
| number of pages
| |
| http://purl.org/ne...btex#hasPublisher
| |
| https://schema.org/isbn
| |
| http://localhost/t...ganizacniJednotka
| |
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