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  • Recently we have observed, that behavior of many contemporary logic synthesis and optimization processes depends on variable ordering in their input; they produce different results for different variable orderings. This fact can be exploited to escape local optima in the iterative resynthesis process, where individual synthesis and optimization steps are run repeatedly, in order to gradually improve the solution quality. In this paper we show an experimental analysis of influence of variable ordering on the result quality, for different synthesis steps in ABC. Next, we present a method of using random permutations of variables in the overall iterative synthesis process, in order to improve the result quality. Experimental evaluation using both standard benchmarks and industrial circuits is presented, to show the viability of the concept.
  • Recently we have observed, that behavior of many contemporary logic synthesis and optimization processes depends on variable ordering in their input; they produce different results for different variable orderings. This fact can be exploited to escape local optima in the iterative resynthesis process, where individual synthesis and optimization steps are run repeatedly, in order to gradually improve the solution quality. In this paper we show an experimental analysis of influence of variable ordering on the result quality, for different synthesis steps in ABC. Next, we present a method of using random permutations of variables in the overall iterative synthesis process, in order to improve the result quality. Experimental evaluation using both standard benchmarks and industrial circuits is presented, to show the viability of the concept. (en)
Title
  • On Using Permutation of Variables to Improve the Iterative Power of Resynthesis
  • On Using Permutation of Variables to Improve the Iterative Power of Resynthesis (en)
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  • On Using Permutation of Variables to Improve the Iterative Power of Resynthesis
  • On Using Permutation of Variables to Improve the Iterative Power of Resynthesis (en)
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  • RIV/68407700:21240/12:00195075!RIV13-MSM-21240___
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  • 156504
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  • RIV/68407700:21240/12:00195075
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  • logic synthesis; resynthesis; iterative processes; permutation (en)
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  • [B6839D5BD77F]
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  • Freiberg
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  • Freiberg
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  • Proc. of 10th International Workshop on Boolean Problems
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  • Fišer, Petr
  • Schmidt, Jan
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  • Technische Universität Bergakademie
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  • 978-3-86012-438-3
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  • 21240
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