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Description
  • This paper presents a new optimization tool for analog circuit design. The proposed tool is based on the robust version of the differential evolution optimization method. Corners of technology, temperature, voltage and current supplies are taken into account during the optimization. That ensures robust resulting circuits. Those circuits usually do not need any schematic change and are ready for the layout. The newly developed tool is implemented directly to the Cadence design environment to achieve very short setup time of the optimization task. The design automation procedure was enhanced by optimization watchdog feature. It was created to control optimization progress and moreover to reduce the search space to produce better design in shorter time. The optimization algorithm presented in this paper was successfully tested on several design examples.
  • This paper presents a new optimization tool for analog circuit design. The proposed tool is based on the robust version of the differential evolution optimization method. Corners of technology, temperature, voltage and current supplies are taken into account during the optimization. That ensures robust resulting circuits. Those circuits usually do not need any schematic change and are ready for the layout. The newly developed tool is implemented directly to the Cadence design environment to achieve very short setup time of the optimization task. The design automation procedure was enhanced by optimization watchdog feature. It was created to control optimization progress and moreover to reduce the search space to produce better design in shorter time. The optimization algorithm presented in this paper was successfully tested on several design examples. (en)
Title
  • A powerful optimization tool for analog integrated circuits design
  • A powerful optimization tool for analog integrated circuits design (en)
skos:prefLabel
  • A powerful optimization tool for analog integrated circuits design
  • A powerful optimization tool for analog integrated circuits design (en)
skos:notation
  • RIV/68407700:21230/13:00212883!RIV14-MSM-21230___
http://linked.open...avai/predkladatel
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(VG20102015015), S
http://linked.open...iv/cisloPeriodika
  • 3
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 58954
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/13:00212883
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • Analog circuit synthesis; optimization tool; differential evolution; search space; optimization watchdog (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...odStatuVydavatele
  • CZ - Česká republika
http://linked.open...ontrolniKodProRIV
  • [AA349415CCEA]
http://linked.open...i/riv/nazevZdroje
  • Radioengineering
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...v/svazekPeriodika
  • 22
http://linked.open...iv/tvurceVysledku
  • Jakovenko, Jiří
  • Kubař, Miloslav
http://linked.open...ain/vavai/riv/wos
  • 000324900200033
issn
  • 1210-2512
number of pages
http://localhost/t...ganizacniJednotka
  • 21230
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