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  • Current video surveillance applications put higher demand both on processing power and personal privacy. This results in new video processing solutions being based on smart cameras. This paper presents a sample implementation of a system that implements core functions of a smart camera - motion detection and labelling - in an FPGA. The implementation is based on the data-flow ASVP platform extended with a number of selection operations that enable to implement constructs with conditional branching. Experimental performance results and power consumption data are presented for an actual implementation in the Xilinx SP605 board.
  • Current video surveillance applications put higher demand both on processing power and personal privacy. This results in new video processing solutions being based on smart cameras. This paper presents a sample implementation of a system that implements core functions of a smart camera - motion detection and labelling - in an FPGA. The implementation is based on the data-flow ASVP platform extended with a number of selection operations that enable to implement constructs with conditional branching. Experimental performance results and power consumption data are presented for an actual implementation in the Xilinx SP605 board. (en)
Title
  • Video Surveillance Application Based on Application Specific Vector Processors
  • Video Surveillance Application Based on Application Specific Vector Processors (en)
skos:prefLabel
  • Video Surveillance Application Based on Application Specific Vector Processors
  • Video Surveillance Application Based on Application Specific Vector Processors (en)
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  • RIV/67985556:_____/12:00382184!RIV13-MSM-67985556
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  • I, P(7H10001)
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  • 177447
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  • RIV/67985556:_____/12:00382184
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  • video surveillance; smart camera; custom accelerators; vector processing; FPGA (en)
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  • [8E5B6B1F01BB]
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  • Karlsruhe
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  • Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing
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  • Daněk, Martin
  • Kohout, Lukáš
  • Sýkora, Jaroslav
  • Honzík, P.
  • Bartosinski, Roman
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number of pages
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  • Electronic Chips & Systems design Initiative
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  • 978-2-9539987-2-6
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