About: DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION

Facets (new session)
Description
Metadata
Settings
- owl:sameAs
- Inference Rule:

About: DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION Goto Sponge NotDistinct Permalink

An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

Attributes	Values
rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Článek popisuje kroky při návrhu decimačního filtru v jazyce VHDL pro vícebitový sigma-delta modulátor. Parametry decimačního filtru jsou odvozeny ze specifikace vícebitového sigma-delta modulátoru se dvěma kroky kvantovacího procesu. Návrh decimačního filtru byl proveden teoreticky v programu Matlab. Výsledná implementace byla provedena v obvodu Xilinx FPGA Spartan 3 XC3S200-5FT256. (cs) This paper describes steps involved in a VHDL design of digital decimation filter for multibit sigma-delta (ΣΔ) modulator. Parameters of decimation filter are derived from the specification of the multibit Σ∆ modulator with two-step quantization architecture. Using Matlabtool it is possible to find the filter order, the required quantizationlevel for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The design is programmed and tested on a Xilinx FPGA –Spartan 3 XC3S200-5FT256. This paper describes steps involved in a VHDL design of digital decimation filter for multibit sigma-delta (ΣΔ) modulator. Parameters of decimation filter are derived from the specification of the multibit Σ∆ modulator with two-step quantization architecture. Using Matlabtool it is possible to find the filter order, the required quantizationlevel for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The design is programmed and tested on a Xilinx FPGA –Spartan 3 XC3S200-5FT256. (en)
Title	DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION Návrh decimačního filtru pro vícebitový sigma-delta modulátor se dvěma kroky kvantovacího procesu. (cs) DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION (en)
skos:prefLabel	DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION Návrh decimačního filtru pro vícebitový sigma-delta modulátor se dvěma kroky kvantovacího procesu. (cs) DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION (en)
skos:notation	RIV/00216305:26220/06:PU63772!RIV07-GA0-26220___
http://linked.open.../vavai/riv/strany	83-86
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GA102/05/0869), Z(MSM0021630503)
http://linked.open...vai/riv/dodaniDat	2007
http://linked.open...aciTvurceVysledku	Fujcik, Lukáš Mougel, Thibault
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta elektrotechniky a komunikačních technologií
http://linked.open...dnocenehoVysledku	470940
http://linked.open...ai/riv/idVysledku	RIV/00216305:26220/06:PU63772
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	decimation filter, programmable logic device (en)
http://linked.open.../riv/klicoveSlovo	decimation filter programmable logic device
http://linked.open...ontrolniKodProRIV	[584EECD2EF49]
http://linked.open...v/mistoKonaniAkce	Gdynia
http://linked.open...i/riv/mistoVydani	Gdynia
http://linked.open...i/riv/nazevZdroje	Proceedings of the International Conference, Mixed Design of Integrated Circuits and Systems
http://linked.open...in/vavai/riv/obor	JA
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	2 (xsd:int)
http://linked.open...vavai/riv/projekt	New principles of intergrated low-voltage and low-power AD converters in sub-micron technologies
http://linked.open...UplatneniVysledku	2006
http://linked.open...iv/tvurceVysledku	Fujcik, Lukáš Mougel, Thibault
http://linked.open...vavai/riv/typAkce	CST - Celostátní
http://linked.open.../riv/zahajeniAkce	2006-06-22 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Nové trendy v mikroelektronických systémech a nanotechnologiích (MIKROSYN)
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Neuveden
https://schema.org/isbn	83-922632-1-9
http://localhost/t...ganizacniJednotka	26220
is http://linked.open...avai/riv/vysledek of	DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION

Faceted Search & Find service v1.16.118 as of Jun 21 2024

Alternative Linked Data Documents: ODE Content Formats:

RDF

ODATA

Microdata

About

OpenLink Virtuoso version 07.20.3240 as of Jun 21 2024, on Linux (x86_64-pc-linux-gnu), Single-Server Edition (126 GB total memory, 110 GB memory in use)
Data on this page belongs to its respective rights holders.
Virtuoso Faceted Browser Copyright © 2009-2024 OpenLink Software