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  • Verifying VHDL Designs with Multiple Clocks in SMV
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  • RIV/00216224:14330/07:00019329!RIV11-AV0-14330___
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  • Formal Methods Applications and Technology, 11th International Workshop on Formal Methods for Industrial Critical Systems, FMICS 2006, and 5th International Workshop on Parallel and Distributed Methods in Verification, PDMC 2006
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