About: The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. We propose a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. Our sample implementation that supports the Image Segmentation kernel is capable of 332 MFLOPs, 400 MFLOPs, and 250 MFLOPs per coprocessor core in Virtex 5, Virtex 6 and Spartan 6 technologies, respectively. The core size is roughly 1500 slices, depending on the configuration and technology. The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. We propose a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. Our sample implementation that supports the Image Segmentation kernel is capable of 332 MFLOPs, 400 MFLOPs, and 250 MFLOPs per coprocessor core in Virtex 5, Virtex 6 and Spartan 6 technologies, respectively. The core size is roughly 1500 slices, depending on the configuration and technology. (en)
Title	The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor (en)
skos:prefLabel	The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor (en)
skos:notation	RIV/67985556:_____/12:00376595!RIV13-MSM-67985556
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(7H10001), Z(AV0Z10750506)
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Kohout, Lukáš Sýkora, Jaroslav Kafka, Leoš Daněk, Martin Bartosinski, Roman
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Ústav teorie informace a automatizace AV ČR, v. v. i.
http://linked.open...dnocenehoVysledku	123575
http://linked.open...ai/riv/idVysledku	RIV/67985556:_____/12:00376595
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	custom accelerators; vector processing; FPGA (en)
http://linked.open.../riv/klicoveSlovo	FPGA custom accelerators vector processing
http://linked.open...ontrolniKodProRIV	[936DCAEFF514]
http://linked.open...v/mistoKonaniAkce	Tallinn
http://linked.open...i/riv/mistoVydani	Tallinn, ESTONIA
http://linked.open...i/riv/nazevZdroje	Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	5 (xsd:int)
http://linked.open...cetTvurcuVysledku	6 (xsd:int)
http://linked.open...vavai/riv/projekt	Smart Multicore Embedded SYstems
http://linked.open...UplatneniVysledku	2012
http://linked.open...iv/tvurceVysledku	Daněk, Martin Kafka, Leoš Kohout, Lukáš Sýkora, Jaroslav Honzík, P. Bartosinski, Roman
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open...ain/vavai/riv/wos	000312905700020
http://linked.open.../riv/zahajeniAkce	2012-04-18 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Pokročilé matematické metody získávání, zpracování a využití informací a znalostí ve složitých a nedeterministických systémech
number of pages	6 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE
https://schema.org/isbn	978-1-4673-1185-4

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