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  • In current era of complex chip designs targeting wireless mobile terminals, architects and designers need to conform to tight design constraints – both in terms of performance (e.g. execution time, silicon area, energy consumption) and time-to-market. Further, additional flexibility is required in these designs to handle multiple wireless standards, sometimes even concurrently. To achieve these challenging goals, the authors introduce a platform architecture that uses a decentralized control to minimize communication and control overhead while keeping timing predictable by using state-of-the-art components and a novel interconnect. The authors demonstrate three main achievements in running multiple wireless standards on their platform: 1.053Gbps 4x4 80MHz WLAN 802.11ac receiver data path meeting the SIFS timing with a latency of 12.5µs, dual concurrent 173Mbps 2x2 20MHz Cat-4 3GPP-LTE receiver and platform reconfiguration from WLAN 11n receiver to 3GPP-LTE one in 52µs. Further the authors describe the design flow used to prepare main components of our platform architecture for a tape-out, while especially keeping a close eye on energy consumption. We believe that our chip design flow is generic and can be used in other custom processor chip designs even outside wireless domain.
  • In current era of complex chip designs targeting wireless mobile terminals, architects and designers need to conform to tight design constraints – both in terms of performance (e.g. execution time, silicon area, energy consumption) and time-to-market. Further, additional flexibility is required in these designs to handle multiple wireless standards, sometimes even concurrently. To achieve these challenging goals, the authors introduce a platform architecture that uses a decentralized control to minimize communication and control overhead while keeping timing predictable by using state-of-the-art components and a novel interconnect. The authors demonstrate three main achievements in running multiple wireless standards on their platform: 1.053Gbps 4x4 80MHz WLAN 802.11ac receiver data path meeting the SIFS timing with a latency of 12.5µs, dual concurrent 173Mbps 2x2 20MHz Cat-4 3GPP-LTE receiver and platform reconfiguration from WLAN 11n receiver to 3GPP-LTE one in 52µs. Further the authors describe the design flow used to prepare main components of our platform architecture for a tape-out, while especially keeping a close eye on energy consumption. We believe that our chip design flow is generic and can be used in other custom processor chip designs even outside wireless domain. (en)
Title
  • Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication
  • Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication (en)
skos:prefLabel
  • Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication
  • Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication (en)
skos:notation
  • RIV/61989100:27740/13:86087301!RIV14-MSM-27740___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • N
http://linked.open...iv/cisloPeriodika
  • 1
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
  • Palkovič, Martin
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 68577
http://linked.open...ai/riv/idVysledku
  • RIV/61989100:27740/13:86087301
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • WLAN; LTE; Platform Architecture Design; Design Flow; Wireless Systems (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...odStatuVydavatele
  • US - Spojené státy americké
http://linked.open...ontrolniKodProRIV
  • [F0AD66A5EC42]
http://linked.open...i/riv/nazevZdroje
  • International Journal of Embedded and Real-Time Communication Systems
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...UplatneniVysledku
http://linked.open...v/svazekPeriodika
  • 4
http://linked.open...iv/tvurceVysledku
  • Avasare, Prabhat
  • Palkovič, Martin
  • Amin, Amir
  • Declerck, Jeroen
  • Glassee, Miguel
  • Raghavan, Praveen
  • Umans, Erik
issn
  • 1947-3176
number of pages
http://bibframe.org/vocab/doi
  • 10.4018/jertcs.2013010103
http://localhost/t...ganizacniJednotka
  • 27740
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