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rdf:type
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Description
| - In this paper, we present a methodology for generating<br>VHDL descriptions of hardware checkers is presented. It is<br>shown how the methodology can be used to generate on-line<br>checkers of communication protocols, counters, decoders,<br>registers, comparators, etc. It is also demonstrated how a<br>checker for more complex structures can be developed. We<br>describe the possibilities of utilizing this approach in the design<br>of Fault Tolerant Systems (FTS). Experimental results<br>in terms of FPGA resources needed to synthesize different<br>types of checkers are presented.
- In this paper, we present a methodology for generating<br>VHDL descriptions of hardware checkers is presented. It is<br>shown how the methodology can be used to generate on-line<br>checkers of communication protocols, counters, decoders,<br>registers, comparators, etc. It is also demonstrated how a<br>checker for more complex structures can be developed. We<br>describe the possibilities of utilizing this approach in the design<br>of Fault Tolerant Systems (FTS). Experimental results<br>in terms of FPGA resources needed to synthesize different<br>types of checkers are presented. (en)
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Title
| - Digital Systems Architectures Based on On-line Checkers
- Digital Systems Architectures Based on On-line Checkers (en)
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skos:prefLabel
| - Digital Systems Architectures Based on On-line Checkers
- Digital Systems Architectures Based on On-line Checkers (en)
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skos:notation
| - RIV/00216305:26230/08:PU76713!RIV10-MSM-26230___
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http://linked.open...avai/riv/aktivita
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http://linked.open...avai/riv/aktivity
| - P(GD102/05/H050), Z(MSM0021630528)
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http://linked.open...vai/riv/dodaniDat
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http://linked.open...aciTvurceVysledku
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http://linked.open.../riv/druhVysledku
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http://linked.open...iv/duvernostUdaju
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http://linked.open...titaPredkladatele
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http://linked.open...dnocenehoVysledku
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http://linked.open...ai/riv/idVysledku
| - RIV/00216305:26230/08:PU76713
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http://linked.open...riv/jazykVysledku
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http://linked.open.../riv/klicovaSlova
| - Fault Tolerant Systems, simple circuit, checker, FPGA, on-line testing, ,protocols (en)
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http://linked.open.../riv/klicoveSlovo
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http://linked.open...ontrolniKodProRIV
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http://linked.open...v/mistoKonaniAkce
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http://linked.open...i/riv/mistoVydani
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http://linked.open...i/riv/nazevZdroje
| - 11th EUROMICRO Conference on Digital System Design DSD 2008
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http://linked.open...in/vavai/riv/obor
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http://linked.open...ichTvurcuVysledku
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http://linked.open...cetTvurcuVysledku
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http://linked.open...vavai/riv/projekt
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http://linked.open...UplatneniVysledku
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http://linked.open...iv/tvurceVysledku
| - Kotásek, Zdeněk
- Straka, Martin
- Winter, Jan
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http://linked.open...vavai/riv/typAkce
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http://linked.open.../riv/zahajeniAkce
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http://linked.open...n/vavai/riv/zamer
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number of pages
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http://purl.org/ne...btex#hasPublisher
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https://schema.org/isbn
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http://localhost/t...ganizacniJednotka
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