About: An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	We propose a method to efficiently design a %22parity generator%22, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designed by duplicating the original circuit, XOR-ing given groups of its outputs and resynthesizing the whole circuit. The resulting circuitry is mostly smaller than the original circuit. The major task to be solved is to properly select the groups of outputs to be XORed to obtain multiple parity bits and maximally reduce the generator size. A method based on principles of the FC-Min minimizer is proposed in this paper. The parity generator is exploited in on line diagnostics, to design self-checking circuits based on a modified duplex system. We propose a method to efficiently design a %22parity generator%22, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designed by duplicating the original circuit, XOR-ing given groups of its outputs and resynthesizing the whole circuit. The resulting circuitry is mostly smaller than the original circuit. The major task to be solved is to properly select the groups of outputs to be XORed to obtain multiple parity bits and maximally reduce the generator size. A method based on principles of the FC-Min minimizer is proposed in this paper. The parity generator is exploited in on line diagnostics, to design self-checking circuits based on a modified duplex system. (en)
Title	An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA (en)
skos:prefLabel	An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA (en)
skos:notation	RIV/68407700:21230/08:00145451!RIV10-MSM-21230___
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(FI-IM4/149), Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat	2010
http://linked.open...aciTvurceVysledku	Kubátová, Hana Kubalík, Pavel Fišer, Petr
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta elektrotechnická
http://linked.open...dnocenehoVysledku	355644
http://linked.open...ai/riv/idVysledku	RIV/68407700:21230/08:00145451
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	FC-Min; On-line testing; Output grouping; Parity prediction (en)
http://linked.open.../riv/klicoveSlovo	FC-Min On-line testing Output grouping Parity prediction
http://linked.open...ontrolniKodProRIV	[D7607BF31444]
http://linked.open...v/mistoKonaniAkce	Parma
http://linked.open...i/riv/mistoVydani	Los Alamitos
http://linked.open...i/riv/nazevZdroje	Proceedings of 11th Euromicro Conference on Digital System Design
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	*Research and Development of High-rate Microwave Line Featured by QAM Modulation and the Transmission Speed of 155 Mbit/s.
http://linked.open...UplatneniVysledku	2008
http://linked.open...iv/tvurceVysledku	Kubátová, Hana Kubalík, Pavel Fišer, Petr
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2008-09-03 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum perspektivních informačních a komunikačních technologií
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-0-7695-3277-6
http://localhost/t...ganizacniJednotka	21230
is http://linked.open...avai/riv/vysledek of	An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA

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