About: A High-Level Design Approach Towards FPGA-based Filter Design

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	Není k dispozici (cs) A case-study FPGA implementation of the Laguerre filter using the Xilinx System Generator for DSP is presented in the paper. The properties of the Laguerre filter make it attractive for modeling systems with long impulse response. The advantage of using the System Generator is that it is possible to use the high-level Simulink environment not only for the algorithm prototyping, but also to generate the corresponding VHDL code, reducing thus the need for manual recording. A case-study FPGA implementation of the Laguerre filter using the Xilinx System Generator for DSP is presented in the paper. The properties of the Laguerre filter make it attractive for modeling systems with long impulse response. The advantage of using the System Generator is that it is possible to use the high-level Simulink environment not only for the algorithm prototyping, but also to generate the corresponding VHDL code, reducing thus the need for manual recording. (en)
Title	Není k dispozici (cs) A High-Level Design Approach Towards FPGA-based Filter Design A High-Level Design Approach Towards FPGA-based Filter Design (en)
skos:prefLabel	Není k dispozici (cs) A High-Level Design Approach Towards FPGA-based Filter Design A High-Level Design Approach Towards FPGA-based Filter Design (en)
skos:notation	RIV/68407700:21230/04:03105587!RIV/2005/MSM/212305/N
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(LN00B096)
http://linked.open...vai/riv/dodaniDat	2005
http://linked.open...aciTvurceVysledku	Bartosinski, Roman
http://linked.open.../riv/druhVysledku	A(V) - Audiovizuální tvorba se vzdáleným přístupem
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta elektrotechnická
http://linked.open...dnocenehoVysledku	552939
http://linked.open...ai/riv/idVysledku	RIV/68407700:21230/04:03105587
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Laguerre filter; DSP; FPGA; codesign; simulation (en)
http://linked.open.../riv/klicoveSlovo	codesign FPGA simulation Laguerre filter DSP
http://linked.open...i/riv/kodPristupu	L
http://linked.open...ontrolniKodProRIV	[E5B2B002D379]
http://linked.open...i/riv/mistoVydani	Praha
http://linked.open...n/vavai/riv/nosic	neuvedeno
http://linked.open...in/vavai/riv/obor	BC
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	Center for Applied Cybernetics
http://linked.open...UplatneniVysledku	2004
http://linked.open...iv/tvurceVysledku	Bartosinski, Roman Líčko, M. Kühl, M.
http://localhost/t...ganizacniJednotka	21230

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