About: Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties

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Description	The paper presents testability analysis method that is based on partitioning circuit under analysis (CUA) into testable blocks (TBs). The concept of TBs is further utilized for power consumption reduction during the test application. Software tools which were developed during the research and integrated into the third party design flow are also described. The experimental results gained from the application of the methodology on selected benchmarks and practical designs are demonstrated. It was proven on the benchmarks, used for the verification of the methodology, that a fault coverage comparable to the partial scan method can be obtained. When combined with test vectors/scan cells reordering methodology significant power savings can be reached. The paper presents testability analysis method that is based on partitioning circuit under analysis (CUA) into testable blocks (TBs). The concept of TBs is further utilized for power consumption reduction during the test application. Software tools which were developed during the research and integrated into the third party design flow are also described. The experimental results gained from the application of the methodology on selected benchmarks and practical designs are demonstrated. It was proven on the benchmarks, used for the verification of the methodology, that a fault coverage comparable to the partial scan method can be obtained. When combined with test vectors/scan cells reordering methodology significant power savings can be reached. (en)
Title	Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties (en)
skos:prefLabel	Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties (en)
skos:notation	RIV/00216305:26230/08:PU76768!RIV10-MSM-26230___
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(GD102/05/H050), Z(MSM0021630528)
http://linked.open...iv/cisloPeriodika	5
http://linked.open...vai/riv/dodaniDat	2010
http://linked.open...aciTvurceVysledku	Kotásek, Zdeněk Herrman, Tomáš Škarvada, Jaroslav
http://linked.open.../riv/druhVysledku	J - Článek v odborném periodiku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	399660
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/08:PU76768
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Testable block, Circuit partitioning, Test vectors reordering, Scan cells reordering, Low power (en)
http://linked.open.../riv/klicoveSlovo	Low power Circuit partitioning Scan cells reordering Test vectors reordering Testable block
http://linked.open...odStatuVydavatele	NL - Nizozemsko
http://linked.open...ontrolniKodProRIV	[09BB33B3EA6D]
http://linked.open...i/riv/nazevZdroje	Microprocessors and Microsystems
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	Integrated Approach to Education of PhD Students in the Area of Parallel and Distributed Systems
http://linked.open...UplatneniVysledku	2008
http://linked.open...v/svazekPeriodika	32
http://linked.open...iv/tvurceVysledku	Kotásek, Zdeněk Škarvada, Jaroslav Herrman, Tomáš
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
issn	0141-9331
number of pages	7 (xsd:int)
http://localhost/t...ganizacniJednotka	26230
is http://linked.open...avai/riv/vysledek of	Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties

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