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rdf:type
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Description
| - Our backward-determining structure generates all valid input vectors to an applied output vector, an input vector is generated during only one clock cycle, two variants of reconfiguration for speeding up the vector generation, experimental data obtained for ISCAS'85. Reconfiguration usage for small circuits is not effective enough (average area overhead is about 120 %, average speed up is about 9.3 %), but for large circuits is acceptable (average area overhead is about 96 %, average speed up is about 21.5 %).
- Our backward-determining structure generates all valid input vectors to an applied output vector, an input vector is generated during only one clock cycle, two variants of reconfiguration for speeding up the vector generation, experimental data obtained for ISCAS'85. Reconfiguration usage for small circuits is not effective enough (average area overhead is about 120 %, average speed up is about 9.3 %), but for large circuits is acceptable (average area overhead is about 96 %, average speed up is about 21.5 %). (en)
- Námi navr3ená zpitni-odvozující struktura generuje v1echny platné vstupní vektory k poilo3enému výstupnímu vektoru, vstupní vektor je generován bihem pouze jednoho hodinového cyklu, dvi varianty rekonfigurace pro zrychlení generování vektoru, experimentální data získána nad ISCAS'85. Vyu3ití rekonfigurace pro malé obvody není dostateeni efektivní (prumirná prostorová slo3itost je okolo 120 %, prumirné zrychlení je v1ak pouze okolo 9,3 %), ale pro velké obvody je poijatelný (prumirná prostorová slo3itost je okolo 96 %, prumirné zrychlení je okolo 21,5 %). (cs)
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Title
| - Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process
- Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process (en)
- Rekonfigurace backtrace algoritmu implementovaného v HW pro zrychlení procesu generování vektoru (cs)
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skos:prefLabel
| - Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process
- Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process (en)
- Rekonfigurace backtrace algoritmu implementovaného v HW pro zrychlení procesu generování vektoru (cs)
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skos:notation
| - RIV/68407700:21230/06:03119432!RIV07-GA0-21230___
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http://linked.open.../vavai/riv/strany
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http://linked.open...avai/riv/aktivita
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http://linked.open...avai/riv/aktivity
| - P(GA102/04/2137), Z(MSM6840770014)
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http://linked.open...vai/riv/dodaniDat
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http://linked.open...aciTvurceVysledku
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http://linked.open.../riv/druhVysledku
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http://linked.open...iv/duvernostUdaju
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http://linked.open...titaPredkladatele
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http://linked.open...dnocenehoVysledku
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http://linked.open...ai/riv/idVysledku
| - RIV/68407700:21230/06:03119432
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http://linked.open...riv/jazykVysledku
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http://linked.open.../riv/klicovaSlova
| - backtrace; hardware; reconfiguration; scan design; vector generation (en)
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http://linked.open.../riv/klicoveSlovo
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http://linked.open...ontrolniKodProRIV
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http://linked.open...v/mistoKonaniAkce
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http://linked.open...i/riv/mistoVydani
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http://linked.open...i/riv/nazevZdroje
| - Proceedings of the 2006 IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics
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http://linked.open...in/vavai/riv/obor
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http://linked.open...ichTvurcuVysledku
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http://linked.open...cetTvurcuVysledku
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http://linked.open...vavai/riv/projekt
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http://linked.open...UplatneniVysledku
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http://linked.open...iv/tvurceVysledku
| - Novák, Ondřej
- Šťáva, Martin
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http://linked.open...vavai/riv/typAkce
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http://linked.open.../riv/zahajeniAkce
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http://linked.open...n/vavai/riv/zamer
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number of pages
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http://purl.org/ne...btex#hasPublisher
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https://schema.org/isbn
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http://localhost/t...ganizacniJednotka
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