About: Relocation of reconfigurable modules on Xilinx FPGA

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
rdfs:seeAlso	http://apps.webofknowledge.com/full_record.do?product=UA&search_mode=GeneralSearch&qid=9&SID=V2ZZlanTQqUyFdhYYcD&page=1&doc=1
Description	This paper presents a design flow that allows relocation of reconfigurable modules on Xilinx FPGAs using dynamic partial reconfiguration (DPR). Relocation of these modules is performed without requirements of re-implementing the design. The article describes the relocation procedure based on modifications of major address of the partial configuration bitstream. This approach allows using single partial bitstream for multiple areas in FPGA device. It reduces a number of partial bitstreams stored in memory, saves the implementation time and it can increase dependability of the system. The proposed flow is demonstrated on a simple example with multiplier and adder locations mutually exchanged. This paper presents a design flow that allows relocation of reconfigurable modules on Xilinx FPGAs using dynamic partial reconfiguration (DPR). Relocation of these modules is performed without requirements of re-implementing the design. The article describes the relocation procedure based on modifications of major address of the partial configuration bitstream. This approach allows using single partial bitstream for multiple areas in FPGA device. It reduces a number of partial bitstreams stored in memory, saves the implementation time and it can increase dependability of the system. The proposed flow is demonstrated on a simple example with multiplier and adder locations mutually exchanged. (en)
Title	Relocation of reconfigurable modules on Xilinx FPGA Relocation of reconfigurable modules on Xilinx FPGA (en)
skos:prefLabel	Relocation of reconfigurable modules on Xilinx FPGA Relocation of reconfigurable modules on Xilinx FPGA (en)
skos:notation	RIV/46747885:24220/13:#0002863!RIV14-MSM-24220___
http://linked.open...avai/riv/aktivita	P S
http://linked.open...avai/riv/aktivity	P(LD13019), S
http://linked.open...vai/riv/dodaniDat	2014
http://linked.open...aciTvurceVysledku	Rozkovec, Martin Novák, Ondřej Drahoňovský, Tomáš
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Technická univerzita v Liberci / Fakulta mechatroniky, informatiky a mezioborových studií
http://linked.open...dnocenehoVysledku	102299
http://linked.open...ai/riv/idVysledku	RIV/46747885:24220/13:#0002863
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	FPGA partial reconfiguration (en)
http://linked.open.../riv/klicoveSlovo	FPGA partial reconfiguration
http://linked.open...ontrolniKodProRIV	[4B670C6E198C]
http://linked.open...v/mistoKonaniAkce	Karlovy Vary; Czech Republic
http://linked.open...i/riv/nazevZdroje	16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	Improvement in Reliability of Nano-scale circuits
http://linked.open...UplatneniVysledku	2013
http://linked.open...iv/tvurceVysledku	Novák, Ondřej Rozkovec, Martin Drahoňovský, Tomáš
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2013-01-01 (xsd:date)
number of pages	6 (xsd:int)
http://bibframe.org/vocab/doi	10.1109/DDECS.2013.6549812
http://purl.org/ne...btex#hasPublisher	IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
https://schema.org/isbn	978-1-4673-6135-4
http://localhost/t...ganizacniJednotka	24220

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