About: Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented. In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented. (en)
Title	Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA (en)
skos:prefLabel	Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA (en)
skos:notation	RIV/00216305:26230/10:PU89630!RIV11-GA0-26230___
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(GA102/09/1668), P(GD102/09/H042), S, Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2011
http://linked.open...aciTvurceVysledku	Straka, Martin Kotásek, Zdeněk Kaštil, Jan
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	260383
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/10:PU89630
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	FPGA, partial reconfiguration, controller, fault tolerant system, architecture (en)
http://linked.open.../riv/klicoveSlovo	FPGA architecture - theory of architecture - empathy theory - style fault tolerant system partial reconfiguration controller
http://linked.open...ontrolniKodProRIV	[AB06607CEA30]
http://linked.open...v/mistoKonaniAkce	Tampere
http://linked.open...i/riv/mistoVydani	Tampere
http://linked.open...i/riv/nazevZdroje	NORCHIP 2010
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	SoC circuits reliability and availability improvement Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems
http://linked.open...UplatneniVysledku	2010
http://linked.open...iv/tvurceVysledku	Kaštil, Jan Kotásek, Zdeněk Straka, Martin
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2010-11-15 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	4 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-1-4244-8971-8
http://localhost/t...ganizacniJednotka	26230

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