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rdf:type
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Description
| - In this presentation, a methodology of FTS design based on FPGA is<br>presented. The FT architectures are based both on duplex and TMR<br>systems to which fault detection capabilities are added, the use<br>of on-line checkers for this purpose is demonstrated. It is<br>described how reliability and availability parameters in TMR and<br>duplex structures with checkers can be increased. To demonstrate<br>this, analytical calculations based on Markov reliability model<br>are used. It is also shown how the availability parameters can be<br>affected by the operating environment into which the FTS is<br>implemented. Finally, the results of research and the comparison<br>of our approach with classical TMR and duplex architectures for<br>different failure rates are presented.
- In this presentation, a methodology of FTS design based on FPGA is<br>presented. The FT architectures are based both on duplex and TMR<br>systems to which fault detection capabilities are added, the use<br>of on-line checkers for this purpose is demonstrated. It is<br>described how reliability and availability parameters in TMR and<br>duplex structures with checkers can be increased. To demonstrate<br>this, analytical calculations based on Markov reliability model<br>are used. It is also shown how the availability parameters can be<br>affected by the operating environment into which the FTS is<br>implemented. Finally, the results of research and the comparison<br>of our approach with classical TMR and duplex architectures for<br>different failure rates are presented. (en)
|
Title
| - Reliability Models for Fault Tolerant Architectures Based on FPGA
- Reliability Models for Fault Tolerant Architectures Based on FPGA (en)
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skos:prefLabel
| - Reliability Models for Fault Tolerant Architectures Based on FPGA
- Reliability Models for Fault Tolerant Architectures Based on FPGA (en)
|
skos:notation
| - RIV/00216305:26230/09:PU82705!RIV10-MSM-26230___
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http://linked.open...avai/riv/aktivita
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http://linked.open...avai/riv/aktivity
| - P(GD102/09/H042), Z(MSM0021630528)
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http://linked.open...vai/riv/dodaniDat
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http://linked.open...aciTvurceVysledku
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http://linked.open.../riv/druhVysledku
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http://linked.open...iv/duvernostUdaju
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http://linked.open...titaPredkladatele
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http://linked.open...dnocenehoVysledku
| |
http://linked.open...ai/riv/idVysledku
| - RIV/00216305:26230/09:PU82705
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http://linked.open...riv/jazykVysledku
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http://linked.open.../riv/klicovaSlova
| - TMR, checker, fault tolerant system, reliability model, availability, FPGA (en)
|
http://linked.open.../riv/klicoveSlovo
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http://linked.open...ontrolniKodProRIV
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http://linked.open...v/mistoKonaniAkce
| |
http://linked.open...i/riv/mistoVydani
| |
http://linked.open...i/riv/nazevZdroje
| - 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
|
http://linked.open...in/vavai/riv/obor
| |
http://linked.open...ichTvurcuVysledku
| |
http://linked.open...cetTvurcuVysledku
| |
http://linked.open...vavai/riv/projekt
| |
http://linked.open...UplatneniVysledku
| |
http://linked.open...iv/tvurceVysledku
| - Kotásek, Zdeněk
- Straka, Martin
|
http://linked.open...vavai/riv/typAkce
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http://linked.open.../riv/zahajeniAkce
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http://linked.open...n/vavai/riv/zamer
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number of pages
| |
http://purl.org/ne...btex#hasPublisher
| - Masarykova univerzita. Fakulta informatiky
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https://schema.org/isbn
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http://localhost/t...ganizacniJednotka
| |