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  • In the paper, it is shown how testability analysis can be utilized both to modify digital data path in order to maximally enhance its testability at minimal costs and to offer information applicable during automated synthesis of a controller used to apply a test to the modified data path.  Our method takes a circuit structure described by means of a net-list as an input. The net-list contains information about how instances of particular module types defined in component libraries are interconnected by means of their interfaces. In both the library and net-list, module types belonging to various description levels (gate, register-transfer, system-on-a-chip etc.) can be placed in order to model multilevel or mixed designs. At the output of the method, modified data path and corresponding controller are produced.
  • In the paper, it is shown how testability analysis can be utilized both to modify digital data path in order to maximally enhance its testability at minimal costs and to offer information applicable during automated synthesis of a controller used to apply a test to the modified data path.  Our method takes a circuit structure described by means of a net-list as an input. The net-list contains information about how instances of particular module types defined in component libraries are interconnected by means of their interfaces. In both the library and net-list, module types belonging to various description levels (gate, register-transfer, system-on-a-chip etc.) can be placed in order to model multilevel or mixed designs. At the output of the method, modified data path and corresponding controller are produced. (en)
Title
  • Testability Analysis Driven Data Path Modification And Controller Synthesis
  • Testability Analysis Driven Data Path Modification And Controller Synthesis (en)
skos:prefLabel
  • Testability Analysis Driven Data Path Modification And Controller Synthesis
  • Testability Analysis Driven Data Path Modification And Controller Synthesis (en)
skos:notation
  • RIV/00216305:26230/09:PU82663!RIV10-MSM-26230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
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  • 345979
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26230/09:PU82663
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  • controller, data path, digital circuit, modification, library, netlist, synthesis, test, testability analysis (en)
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http://linked.open...ontrolniKodProRIV
  • [611F9FC015C4]
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  • Brno
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  • Brno
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  • Proceedings of 16th Electronic Devices and Systems IMAPS CS International Conference
http://linked.open...in/vavai/riv/obor
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  • Růžička, Richard
  • Strnadel, Josef
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
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  • Vysoké učení technické v Brně
https://schema.org/isbn
  • 978-80-214-3933-7
http://localhost/t...ganizacniJednotka
  • 26230
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