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  • Paper presents the optimized implementation of the digital signal processing algorithms (real and complex Fast Fourier Transforms) for the specific hardware architecture. The algorithms' source codes were optimized at low level, while all redundant operations (e.g. branching instructions) were avoided. Contrary to results compiled from the high level codes, time consuming load/store operations were considerably eliminated as well and temporal data were stored in the general purpose registers. Contrary to other implementations, the several calls of the identical functions (but with shared data) provide a~reducing of the processor idle states. The TMS320C6748 and TMS320C6678 digital signal processors with the Very Long Instruction Word architecture were used for the implementation of proposed functions. The average duration of FFT optimized functions is between five CPU cycles for four real values and 44 CPU cycles for sixteen real values, respectively.
  • Paper presents the optimized implementation of the digital signal processing algorithms (real and complex Fast Fourier Transforms) for the specific hardware architecture. The algorithms' source codes were optimized at low level, while all redundant operations (e.g. branching instructions) were avoided. Contrary to results compiled from the high level codes, time consuming load/store operations were considerably eliminated as well and temporal data were stored in the general purpose registers. Contrary to other implementations, the several calls of the identical functions (but with shared data) provide a~reducing of the processor idle states. The TMS320C6748 and TMS320C6678 digital signal processors with the Very Long Instruction Word architecture were used for the implementation of proposed functions. The average duration of FFT optimized functions is between five CPU cycles for four real values and 44 CPU cycles for sixteen real values, respectively. (en)
Title
  • Low Level Source Code Optimizing for Single/Multi/core Digital Signal Processors
  • Low Level Source Code Optimizing for Single/Multi/core Digital Signal Processors (en)
skos:prefLabel
  • Low Level Source Code Optimizing for Single/Multi/core Digital Signal Processors
  • Low Level Source Code Optimizing for Single/Multi/core Digital Signal Processors (en)
skos:notation
  • RIV/00216305:26220/13:PU104160!RIV15-MSM-26220___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(ED2.1.00/03.0072), P(EE2.3.20.0007), S
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 85472
http://linked.open...ai/riv/idVysledku
  • RIV/00216305:26220/13:PU104160
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • digital signal processors, parallel architectures, floating-point arithmetic, Fourier transforms, discrete cosine transforms, high performance computing (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [65F291BFDF9F]
http://linked.open...v/mistoKonaniAkce
  • Pardubice
http://linked.open...i/riv/mistoVydani
  • Neuveden
http://linked.open...i/riv/nazevZdroje
  • MAREW 2013
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Frýza, Tomáš
  • Mego, Roman
http://linked.open...vavai/riv/typAkce
http://linked.open...ain/vavai/riv/wos
  • 000326877900052
http://linked.open.../riv/zahajeniAkce
number of pages
http://purl.org/ne...btex#hasPublisher
  • Neuveden
https://schema.org/isbn
  • 978-1-4673-5517-9
http://localhost/t...ganizacniJednotka
  • 26220
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